Semiconductor memory devices are becoming more and more complex as their size decreases and their storage density increases. To help handle some of the increase in storage density, an architecture comprising multiple subarrays of memory cells on a die for storing values such as bits, has been adopted in dynamic random access memory (DRAM) devices. Each of the subarrays comprises multiple rows of memory cells that are accessed or "fired" by activation of row address signals. Each memory cell in a row in a subarray is coupled via a digit line to its own set of interleaved sense amplifiers which provide the bits to pairs of I/O lines 112, 114, 116 and 118, as shown in prior art FIG. 1. FIG. 1 is an example of a complex twist digit line scheme which helps to reduce coupling terms from each digit line to other digit lines. Each digit line twist occupies valuable silicon area, so efficient twist schemes must be utilized. Column decoder lines 120 and 122 run over a block of memory cells on metal, and connect to I/O switches 124 which enable the sense amplifier to provide a bit or digit sensed and amplified from the digit lines to the I/O lines. Due to layout considerations, a global column decode or coldec line usually allows for two digits in every interleaved sense amplifier block to connect to the I/O lines. Thus, one global column decoder line going high allows four adjacent digits or bits of data to be switched onto four I/O line pairs as seen in prior art FIG. 1.
This type of architecture has been very helpful in obtaining DRAMs beyond the 16 MB generation. However, one global column decoder line going high allows four adjacent digits to be switched onto four I/O line pairs. Note that no other global coldec line can go high along these I/O lines, since this would short together digit pairs through the I/O switches. In this conventional scheme, it is often desired to take these four active bits of data to individual external output pins referred to as DQ pins, allowing each bit to be read or written simultaneously. Because neighboring digits are very capacitively coupled to each other due to their close proximity, writing these four adjacent pairs simultaneously can lead to poor write times. Furthermore, since every combination among the four digits must be tested for proper operation, significant time and complexity is added to testing.
In the past, these problems have often meant that only two of the four I/O lines are simultaneously routed to DQ pins, and these two are further chosen to be two non-adjacent digit lines. Thus, I/O pairs 112 and 116 would be simultaneously active, while I/O pairs 114 and 118 were ignored. The opposite is true when 114 and 118 are active, 112 and 116 are ignored. This solves the write problem, but means that another two bits of data must be taken from another array on the die, which adds to die operating current, size, and complexity, all of which adversely affect cost.
There is a need for increasing the number of simultaneous I/O lines which can be output from a memory array. There is a need for this number to be increased without adding to die operating current, size or complexity. There is a further need to cut down on the time, complexity and expense of testing DRAMs.